VHDL coding in Isim Wave Window

VHDL coding in Isim Wave Window

In the Isim wave window my internal signals and outputs appear green and
as initialized but all of my inputs appear as "UU" even though they are
initialized as well. I am simply trying to add 1 whenever either of the
two inputs are 1. The code synthesizes fine without warnings. Any ideas?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity scoreboard2 is
Port ( clk : in STD_LOGIC;
T1 : in STD_LOGIC;
T2 : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (3 downto 0));
end scoreboard2;
architecture Behavioral of scoreboard2 is
signal output_temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal score1,score2: unsigned(1 downto 0) := "00";
signal score3: unsigned(3 downto 0):= "0000";
begin
proc: process(T1,T2,clk)
begin
if(rising_edge(clk)) then
if(T1 = '1') then
score1 <= score1 + 1;
end if;
if(T2 = '1') then
score2 <= score2 + 1;
end if;
end if;
end process proc;
score3 <= score1 & score2;
output_temp <= STD_LOGIC_VECTOR(score3);
Output <= output_temp;
end Behavioral;